Low dissipation inductance drivers



Aug 22, 1957 w. T. RUSCH ETAL 3,337,748

LOW DISSIPATION INDUCTANCE DRIVERS 4 Tron/ Ey Aug. 22, 1967 Filed Dec.25, 1963 W. T. RUSCH ETAL Low DISSIPATION INDUCTANCE DRIVERS 3Sheets-Sheet 2 z 2 el 4 7mm/Ey Aug. 22, i967 w.-T` RUSCH ETAL 3,337,743

LOW DISSIPATION INDUCTANCE DRIVERS Filed Dec. 25, 1963 3 Sheets-Sheet 3F/, WML/AM 7. RUSCH 7740/1445 E. WOODRUFF 5J/Q57? MURE/DGE BYQQM ATORA/Y United Sttes LOW DISSIPATION INDUCTANCE DRIVERS William T. Rusch,Hollis, and Thomas E. Woodruff and Everett Kittredge, Nashua, N.II.,assgnors to Sanders Associates, Inc., Nashua, N.H., a corporation ofDelaware Filed Dec. 23, 1963, Ser. No. 332,613 21 Claims. (Cl. 307-885)As an example, but not in limitation, we may mention I its use in amagnetic deflection system for cathode ray tubes, wherein it is desiredto deect the beam on either or both axes in a one or a series of steps,and to hold the beam in deected position or positions for predeterminedtime intervals. It may also be used to supply power for sawtoothdeliection.

Again, in example but not in limitation, it may be used in the supplycircuit for Controlled Force solenoids, and in general type solenoidapplications, including tape recorder start-stop application, steppedfilm drive, D.C. motor applications, etc.

The general idea of our invention includes the use of several (two ormore) voltage supplies and appropriate circuitry to drive an inductiveload, and to radically decrease drive power requirements by drawing fromthe lowest voltage supply which is instantaneously required to providethe necessary load current.

Most power supplies, especially those having regulators, operateefiiciently only when energy is being supplied by them, and are notreadily adaptable to the charging process necessary for the recovery ofenergy stored in an inductive load. Additionally, energy will bedistributed unevenly among the energy storage sources if the coilcurrent waveform is not symmetrical about zero. For example, if the coilcurrent is repeatedly raised from zero toa positive value and thenreduced to a zero, energy will be drawn from the positive supply sourceor sourcesduring the buildup of coil current in a positive direction(charging), and fed into the negative source or sources during eachdischarge (return of current to zero). This energy is not lost, but thenonsymmetrical process can lead to varying supply voltages.

The first of the above diiiculties may be overcome by the use ofcapacitors as storage elements which may deliver energy eciently to thecoil or receive energy from it. The second difficulty is overcome byemploying a bilateral energy transfer circuit which keeps the averageenergy and voltage of each capacitor at the desired equilibrium value.This will be more particularly explained with reference to FIGS. 5, 6,and 7.

The features of novelty which we believe to be characteristic of ourinvention are set forth with particularity in the appended claims. Ourinvention itself, however, both as to its fundamental principles and asto its particular embodiments, will best be understood by reference tothe specification and accompanying drawing, in which FIG. 1a is acircuit diagram of a simple form of circuit illustrating the principlesof our invention,

FIG. 1b is a curve of currents, i1 and i2 as ordinates plotted againsttime as abscissa,

FIG. 1c is a similar curve of voltage e as ordinate plotted against timeas abscissa,

FIG. 2a is a circuit diagram of our invention as applied in a cathoderay tube deflection circuit embodying a bias choke and a class Aamplier,

FIG. 2b is a plot of current i1, as ordinate against time t as abscissa,

FIG. 2c is a similar plot of iT against time, wherein l`T=IB``L FIG. 2dis a similar plot of eL against time,

FIG. 2e is a similar plot of i2 `against time,

FIG. 2f is a similar plot of i1 against time,

FIG. 3a is a similar diagram of lour invention as employed with a classB amplifier in one of several possible realizations,

FIG. 3b is a plot of current iL as ordinate vs. time as abscissa,

FIG. 3c is a similar plot of eL vs. time,

FIG. 3d is a similar plot of i4 vs. time,

FIG. 3e is a similar plot of i3 vs. time.

FIG. 3 f is a similar plot of i1 vs. time,

FIG. 3g is a similar plot of i2 vs time,

FIG. 4a is a plot of iL vs. time withour circuit operating as asaw-tooth generator,

FIG. 4b is a similar curve of eL vs. time,

FIG. 4c is a series ofcurves showing the power required by our inventionas compared with conventional circuits,

FIG. 5 is a circuit diagram of another circuit embodying our invention,and

FIGS. 6 and 7 are circuit diagrams of still other embodiments of ourinvention.

Referring now more particular-ly to FIGS. 1a, 1b, and 1c, El and E2represent a pair of direct current voltage sources having their positivesides connected to terminals 10 and 11 respectively, and their negativesides grounded.

Switches 12 and 13, here shown for explanatory purposes `as manualswitches, are actually controlled resistance electronic devices, forexample, transistors, tubes or any other controlled resistance element.The lower sides of switches 12 and 13 are connected to the upperterminal of inductance 14, the lower end of which is grounded. Theresistance shown at 15 may be the resistance of inductance 14, and isnot necessarily a physically separate resistance. The current th-roughswitch 12 is i1; that through switch 13 is i2.

The D.C. voltage e from the upper terminal of inductance 14 to ground,as will be understood, is

di.' e R2 wherein i is the current through inductance 14 and resistance1S, L the inductance of inductance 14, and R the va-lue of resistance15.

When the circuit is put into operation, switch 12 is closed and switch13 is open. Under these conditions, current i1 supplied by source E1builds up from zero, and reaches a predetermined level, I, at time T1 atwhich time switch 12 opens, switch 13 closes, and current i2 flows atthe predetermined value, I, drawn from source E2. As shown in FIG. 1c,source E1 supplies voltage from time zero to time T1, at which time E2supplies a much lower voltage, which need only equal IR. It can bedemonstrated mathematically that for lany time after T1, when holdingcurrent is drawn from source E2, the portion of input power due toholding current drawn by the circuit is reduced in the ratio of E1/E2,without impairing holding.

Referring now to FIG. 201, and enlarging upon the principles of FIG. la,18- represents a transistor having base 1812, collector 18e, and emitter18e. The emitter is connected to the negative terminal of voltage source19, the positive terminal of which is connected to the lower terminal ofinductance 22, which, for example but not in limitation, may be thehorizontal deflection coil of a cathode ray tube.

Diode 2t) has one terminal connected to collector 18C of transistor 18,and the other to collector 21C of transistor 21. The emitter 21e oftransistor 21 is connected to the lower terminal of inductance 22. Forsimplicity, the connections to the base lb of transistor 18 and base 2lbof transistor 2li are omitted. Bias choke 23 has its upper terminalconnected to line 2d., to which the upper terminal `of inductance `22,diode 2Q, and collector 18e of transistor 1.3 are connected. The lowerend of bias choke 23 is connected through voltage source 26 to line 25,to which the lower end of inductance 22, emitter 21e, and

the positive terminal of source 19 are also connected.

The inductance of bias choke 23 is equal to or greater than ten timesthat of inductance 22. The current through inductance 22 is indicated byiL, that owing from the top terminal of bias choke to the left is iT,the current through bias choke .23 is IB, and that owing down throughdiode 20 is i2.

Turning now toV FIGS. 2b, 2c, 2d, 2e, and 2f, the operation of thecircuit is as follows:

Bias current IB cornes from a low voltage, low power supply 26. Becausethe D.C. resistive losses in inductance 22 and bias choke 23 are small,the bias supply 26 is usually of the order of one or two volts.Considering the waveforms in FIGS. 2li-2f, initially (when the circuitis turned on), transistor 123 is biased oif by proper control f its basepotential. The emitter 21e of transistor 21 is connected to another lowvoltage, low power negative supply such as 26', which balances thevoltage drops through diode and transistor 21 so as to keep eL (thevoltage across inductance 22)=0 and thus to insure that iL=0. Inpractice, the small Voltage source 26 connected between emitter 21e andline 25 is desirable to overcome holding losses.

When it is desired to increase iL, transistor 21 is controlled in theproper manner to increase its resistance and thereby lower i2 (and iT).Thus, more of the constant bias current IB Hows through coil 22,increasing iL. The required positive coil voltage, eL, is supplied bythe inductive reaction from bias choke 23; with a high inductance biaschoke, only a very small ZIB/dT is required to generate the necessaryvoltage.

When iL has increased to the required value, transistor 21 is controlledso as to fo-rce eL back to zero (again, small resistive losses areneglected). Thus, iL yremains constant (holds) at its previous valuewith negligible power dissipation, since the holding current iL flowsthrough transistor 21, and not through transistor 13 and source 19. Whenit is desired to reduce iL from its hold level, then, and only then,transistor 18 cornes into action. Transistor 1S is made to conduct (byappropriate base control and without saturating; ysaturation would causeserious storage delay lwhen the time cornes to open transistor 18). Assoon as transistor 18 conducts, eL is forced to be negative and iLreduces i2=0 during this operation because diode 2li is reverse biased.

When iL has been reduced as far as required, transistor 18 is againcommanded to open. At that time, current iT ows through diode 20 andtransistor 21, and transistor 21 losslessly controls the holding of iLat the required Value.

The power saving is apparent from the waveforms in FIGS. 2li-2f,inclusive. If diode 26 and transistor 21 were not used, the averagevalue of input power would be EXE', when diode .20 and transistor 21 areadded to the circuit, input power drops to E Xi. E is the voltage ofsource 19.

Turning now to FIG. 3a, this gure shows some of the principles of ourinvention as applied in a Class B circuit. The particular form of thecircuit is for example only. Other configurations are, of course,possible.

In this instance, as before, 22 represents the inductive CII load,current for which is supplied by transistors 30', 31, 32, or transisor33 depending on load conditions, as will be explained. Collector 30C isconnected to the plus side of the voltage supply, +B. Emitter 30e isconnected to collector 31C, and emitter 31e is connected to -E, thenegative side of the voltage supply. A connection is made from emitter30e and collector 31C to the top terminal of coil 22. Oppositely poleddiodes 35 and 36 lhave one terminal connected to line 34, the other tocollectors 32C and 33C of transistors 32 and 33, respectively. Emitters32e and 33e are connected to lower terminal of coil 22 and to ground.For simplicity, the connections of bases 30b, 31b, 32b and 33b have beenomitted.

The operation of the circuit will be clear from reference to FIGS.31a-3g inclusive; it is similar to that of FIG. 2a. Transistor 30 isallowed to become conductive only when iL (the load current) is greaterthan zero and increasing. At this time, eL (the voltage across load coil22) is positive, so diode 36 keeps transistor 33 from being biased inthe wrong direction. Transistors 31 and 32 are kept nonconducting, byappropriate base control, while transistor 30 is conducting. When iLreaches its prescribed positive level, transistor 30 is also madenonconductive while transistors 31 and 32 are still nonconducting, andthe stored positive current in coil 22 flows through transistor 33.Current iL will theoretically remain at the prescribed positive valueindefinitely; but in practice a low voltage, low power positive supplyconnected to emitter 33e would be adequate to supply the small D.C.losses in transistor 33, diode 36, and coil 22. Coil current iL may beheld at this level or reduced to zero by controlling the resistance oftransistor 33.

Operation is similar when load current is negative. Transistor 31conducts only when iL is negative and going more negative. For allconditions where iL is negative and holding, or negative and decreasingin magnitude, 32 is the only conducting transistor. The considerablesaving of power accomplished by the lossless holding technique is clear.Inspection of FIG. 3a and the waveforms of FIGS. 3b-3g show that withoutthe use of transistors 32 and 33, input power would be EXEZI Withtransistor 32 and 33, input power is EX (IH-IS). Comparison of |Li withH- shows the saving and indicates the usefulness of the technique,especially when long hold times are required.

The waveforms indicate that return to center (i.e., to iL=0) betweenpositions of holding might not always be advantageous from a powerstandpoint. For example, if iL were at current 2I and required to changeto I, this can be accomplished, without power supply drain, by controlof transistor 33. But, if iL were reduced -to zero, additional currentthrough transistor 30 and from the -i-E supply would be required toraise iL back to +I.

The circuits of FIGS. 2a and 3a may be used to generate sawtoothdeflection current, with substantial power savings over conventionalcircuits. Refer now to FIGS. 4a and 4b. FIG. 4a is a plot of iL vs.time, and FIG. 4b a plot of eL vs. time. Time Ts is sweep time, and TFis ilyback time. It can be shown that for the circuit of FIG. 2a (chokecoupled Class A with lossless holding), the power required is Ts-i-TFSimilarly, for the circuit of FIG. 3a, power required is Ll2 TslTF Acomparison of power required for conventional choke coupled Class Acircuits and that required for choke coupled Class A circuits withlossless holding, and of conventional Class B circuits and Class B withlossless holding is shown in FIG. 4c, from which it is clear that thepower saving advantages of lossless holding according to our inventioncan be considerable.

Referring now to FIG. 5, in which we have shown still another embodimentof our invention, em represents the input terminal to which a controlvoltage is applied, which, through resistance 40 is applied todeflection amplifier 41, the output of which is connected to bases 43b,44h, 45b and 46b of transistors 43, 44, 45 and 46.

A relatively high source of voltage E2, which may be of the order of40-50 volts, is provided having its terminal connected through diode 47to collector 43e of transistor 43, and its minus -terminal connectedthrough diode 48 to the collector 46c of transistor 46. Emitter 43e oftransistor 43 is connected to collector 44e of transistor 44, andemitter 44e of transis-tor 44 is connected to the common connection ofdiodes 54 and 55 and to the upper terminal of inductance 22, thedeflection coil. Typical numerical values associated with deiiectionamplifier design are:

L (inductance of deec'tion coil 22)=50ph. r (resistance of coil 22,shown as resistor 57)=0.2 ohm. AfL= amps.

Resistance 57 is -the resis-tance of inductance 22, which is connectedthrough resistance 58 to ground. The common point of resistance 40 andamplifier 41 is connected through resistance 59 to the common point ofinductance 22 and resistance 58. Emitter 45e of transistor 45 isconnected to the common point of diodes 54 and 55, and to the -I-terminal of inductance 22. Collector 45e of transistor 45 is connectedto emitter 46e of transistor 46 and through diode 51 to the minusterminal El of a second and lower source of voltage (about 5 volts).Emitter 43e of transistor 43 and collector 44e of transistor 44 areconnected through diode 50 t-o +E1.

Condenser 52 is connected from the common point of diodes 47 and 54 toground, and condenser 53 is connected from the common point of diodes 48and 55 to ground.

The operation of the circuit is as follows:

When it is desired that iL increase to a positive value I, voltage epincreases to about +E2, turning transistors 43 and 44 on, As alreadydescribed, voltage E2 is significantly greater than E. Under theseconditions diode 50 is reverse biased and nonconducting because emitter43e and collector 44e are approximately at -l-E2. Thus, when coilcurrent is positive and increasing, it flows from source -l-E2 orcapacitor 52 Ithrough transistors 43 and 44.

When iL reaches the desired value +I, voltage ep reduces to a levelbetween zero and +E1. Its value when holding iL at I is approximatelyHrm-H58). The positive holding current of coil 22 is supplied from lowvoltage supply -l-El through diode 50 and transistor 44 instead of lfromthe high voltage source -l-Ez, thereby conserving power. Because thecollector current of transistor 44 flowing through diode 50 clamps theemitter 43e of transistor 43 at the voltage of E1, transistor 43 is cutoff since its base voltage is more negative than its emit-ter voltage.When holding, transistor 44 adjusts to compensate for the'small voltagedifference between supply -i-El and the required holding voltage atdifferent values of positive holding current. When it is desired toreduce iL rfrom +I to a lowe positive level or to zero, voltage ep goesnegative to about -E2. The stored energy in coil 22 produces a negativeinductive voltage reaction which increases in magnitude until diode 55conducts. Transistors 44 land 45 are nonconducting, which leaves onlyone possible path for coil current, i.e., through capacitor 53 and diode55. Thus, the stored energy transfers into capacitor 53, charging thiscapacitor slightly more negative than -E2, which opens diode 48. If theabove process occurred repeatedly, energy would be drained continuallyfrom the -I-E2 supply' and from capacitor S2 and deposited in `capacitor53, causing the Voltage of capacitor 53 to go more negative thanallowable for proper circuit operation. This may be prevented by the useof the circuit of FIG. 6.

Referring now to FIG. 6, this is the same as FIG. 5 as to the elementsenclosed in the dotted line boxes, but, in addition, a pa-th X circuitis provided, comprising transistors 61 and 62, and inductance 63.Transistor 61 has its collector 61e connected to the common point ofdiode 54 and capacitor 52, its emitter 61e to the top of inductance 63(the bottom of which is grounded), its base 61b to a suitable terminal,land its collector 61C and emitter 61e connected through diode 63.Transistor 62 has its base 62b connected to a suitable terminal, itscollector 62e` to Ithe top of coil 63, and its emitter 62e to the commonpoint of diode 55 and capacitor 53. Emitter 62e and collector 62C areconnected through diode 64.

The operation of this addition to the circuit of FIG. 5 is:

Whenever the voltage on capacitor 53 goes below a prescribed negativevalue, transistor 62 is turned on and left on until the voltage ofcapacitor 53 returns to its normal level. The excess energy is absorbedby inductance 63. During this operation, transistor 61 is biased off anddiode 63 is reverse biased. When transistor 62 is turned olf, the energystored in inductance 63 is transferred back to capacitor 52 since exgoes positive and the stored negative iX ows through diode 63 intocapacitor 52.

The process is similar for negative values of current. Sensing resist-or58 and inverse current feedback resistor 59 are used to make Tiotssunder conditions of large loop gain. Suppl-ies -l-E and -E2 arenecessary to provide for small, but real, transistor, `diode andresistive losses.

When energy transfer is such that the voltage on capacitor 53 is morenegative than -E2, supply E2 is nonconducting due to the presence ofdiode 48, and operation of |E2 is similar due to the presence of diode47. Thus, the supplies conduct only as necessary to overcome theirreducible losses.

It will be noted that load Vcurrent flows only through one supply at atime, but can flow through one or more transistors in series. Anadvantage of series connection of the transistors is that they may bedriven from a single point drive, ep, and correct operation occurs.While parallel operation of transistors is also possible, and may offeradvantages in certain instances, it has the disadvantage that a singlepoint drive common to all transistor bases does not appear feasible.

The instantaneous matching of required load voltage to the proper supplyas shown and described herein may be used with -other than inductiveloads. The saving of power is due to the drawing of load current fromthe voltage supply of lowest voltage adequate to meet instantaneous loadrequirements.

In the circuit of FIG. 6, coil 63 is shown in the energy transfercircuit. This could perform the same function as coil 22 (deflection,solenoid force, etc.) in conjunction with coil 22 and still serve itsoriginal purpose of energy transfer. For example, if ix=-L, Whenevercoil 22 too-k a certain amount of energy from capacitor 52, coil 63would take the same a-mount from capacitor 53. When coil 22 feeds itsenergy int-o capacitor 53, coil 63 would feed an equal amount intocapacitor 52, keeping both 52 and 53 charged to the desired values.-Proper polarity connections of coil 22and coil 63 would ensure thattheir joint operation performs the required electromagnetic function.

Our experience indicates that the emitter follower transistor connectionas shown herein, using vPNP and NPN transistors as required, is usuallydesirable for driving inductive loads in current feedback amplifiers,although composite connections are advantageous where output powertransistors of the same type are desirable. Cascaded emitter followersmay also be used.

With the capacitor storage and energy transfer circuits herein shown anddescribed, some of the supplies required by conventional counterpartcircuits may be eliminated. For example, in FIGS. and 6, certainconditions might warrant removal of the -E2 supply. In this casecapacitor 53 would be charged by coil 22 through diode 55, and by coil63 thr-ough diode 64. Elimination of the -Ez supply would be possible ifthe average energy taken from capacitor 53 through transistors 46 and 62equalled that injected through diodes 55 and 64.

Another embodiment of our invention is shown in FIG. 7, which isparticularly adapted lfor use with symmetrical sawtooth waveforms.Assuming that a linear sweep is required when iL is increasing, a largecapacitor 71 is provided whose voltage remains approximately at -i-El.Diode 70 is interposed between -i-El and the top of capacitor 71, whichis connected through diodes 72 and 73 respectively to the collectors 74eand 75e of transistors 74 and 75. The emitters 74e and 75e are connectedto the top of inductance 22, the bottom of which is grounded.

The top of coil 22 is also connected to the emitters 76e and 77e oftransistors 76 and 77 respectively. The collectors 76C and 77C areconnected through diodes 78 and 79 respectively to the top of capacitor80, the lower side of which is grounded. The transistor bases 7411, 75b,and 77b are' connected to a suitable point or points.

The operation of the circuit is:

Transistor 75 conducts when iL is positive and increasing; transistor 76conducts when iL is positive and decreasing. Transistor 77 conducts wheniL is negative and going more negative, and transistor 74 conducts wheniL is negative and going less negative (toward Zero).

Energy is transferred with minimum losses between capacitor 71 and coil22, and between capacitor 80 and coil 22. Flyback, when iL goes from itsmaximum positive value to an equal negative value, can be made to occuras a half-cycle resonant sinusoid if the value ot capacitor 80 is chosenfor this result. Linear yback is attained by making capacitor 80relatively large so that its voltage remains relatively constant andnegative. The diodes in series with the transistors serve to maintain ahigh impedance path when wrong polarity voltage would otherwise beimpressed across the collector-emitter junction of the transistors.

The circuit of this ligure provides for transistor control iL at alltimes, as required for many applications requiring high precision. Forexample, if iL is negative and the coil is discharging toward zerocurrent, the normal path is through transistor 74. Thus, the dischargerate may be reduced by increasing the impedance of transistor 74appropriately. If the discharge rate is too high, transistor 77 can beturned on to draw additional current from the coil, because eL ispositive at that time.

In certain instances requiring less precision, the circuit of FIG. 7 maybe simplified, by omitting transistors 75 and 77 and their associateddiodes 73 `and 79, and by connecting diodes 72 and 78 between thecollector and emitter of transistors 74 and 76, respectively. With thissimplified circuit, transistor 74 conducts positive and increasing coilcurrent; when 74 opens, the stored energy of the coil flows throughcapacitor 80 and diode 7 8. Transistor 76 conducts negative coil currentwhich is going more negative, either resonantly or linearly as alreadydiscussed. When iL is negative and transistor 76 is opened, the storedcoil current iiows through diode 72 into capacitor 71 approximatelylinearly if capacitor 71 is large. Control is ymore limited than withthe circuit of FIG. 7, but could be increased by permitting a biascurrent t0 ow through transistor 76 when diode 72 is conducting. Controlof transistor 76 current above and below this bias level could permitcontrol of z'L when the coil is discharging through diode 72. BiasCurrent through transistor 74 would permit similar control when the coilis discharging through diode 78.

While we have shown and described certain preferred embodiments of ourinvention and the best mode presently known to us for practicing thesame, it will be understood that modifications and changes may be madewithout departing from the spirit and scope of our invention.

What is claimed is:

1. A low loss power supply system comprising, in combination, a sourceof substantially constant current connected to one terminal of a load, adiode connected in series with a first transistor, the seriescombination of said diode and said transistor being connected acrosssaid load, -a second transistor connected in series with a voltagesupply, and said last-na-med series combination being connected inparallel with the series combination of said diode and said firsttransistor.

2. The combination claimed inA claim 21 with means for increasing theresistance of said rst transistor to increase the part of said constantcurrent owing through the load.

3. The combination claimed in claim 21 with means for rendering saidsecond transistor conductive to reduce the load current.

4. The combination claim in claim 21 with means for rendering saidsecond transistor conductive when, and only when, the load current is tobe reduced.

5. The combination claimed in claim 21 with means for increasing theresistance of said first transistor when load current is to beincreased, and for rendering said second transistor conductive when saidload current is to be reduced.

6. The combination claimed in claim 21 with means for causing said firsttransistor to control the voltage developed across an inductive load ina manner to reduce said load voltage to substantially zero when saidload current reaches a predetermined value.

7. A low loss power supply system comprising, in combination, a pair ofdiodes, a first pair of transistors, one of said diodes being seriallyconnected with one of said transistors and the other of said diodesbeing7 seri-ally connected with the other of said transistors, saiddiodes being oppositely poled and connected together at la common point,the combinations of said series-connected diodes and transistors -beingconnected in parallel across a load, a second pair of transistorsconnected in series across a source of voltage, and means connecting thecommon point of said diodes to the connection between said second pairof transistors.

8. The -combination claimed in claim 7 with means for preventing thetransistor connected to the positive side of said voltage source frombecoming conductive except when load current is positive and increasing.

9. The combination claimed in claim 7 with means for permittingconduction of one of said transistors and -for preventing conduction byall other of said transistors during the time said one transistor isconducting.

10. The combin-ation claimed in claim 7 with means for preventing thetransistor connected to the negative side of said voltage source frombecoming conductive except when load current is negative and decreasing.

11. The combination claimed in claim 7 with means for causing conductionin only one of said transistors while preventing conduction in allothers only whe-n load current is negative and decreasing in magnitude.

12. The combination claimed in claim 7 with means for preventingconduction i-n all said transistors except the one having its emitterconnected to the negative source of voltage, when the load current isnegative and going more negative.

13. The combination claimed in claim 7, with means for causing one ofsaid transistors to become conductive only when the load current ispositive and increasing, for causing anOthr of Said transistors tobecome conductive only when the load current is negative and going morenegative, for causing still another of said transistors to becomeconductive only when the load current is negative and holding, or isnegative and decreasing in magnitu-de, and for causing another of saidtransistors to become conductive only when the load cur-rent has adesired value.

14. A low loss rechargeable power supply system comprising, incombination, a load, a pair of storage elements, and a bilateral energytransfer circuit connected between said storage elements and said loadfor delivering energy from said storage elements to said load and forabsorbin-g energy from said load for delivery to said storage elements,said bilateral energy transfer circuit including means for maintainingthe average energy and voltage of each of said storage elements at a`desired equilibrium value.

15. The combination claimed in claim 14 having a pair of rectiers, eachof said rectiers being connected in series between one of said storageelements respectively, and said load.

16. The combination 4claimed in claim 14, wherein said bilateral energy.transfer circuit includes a pair of selectable sources of potential ofdifferent magnitude, and means for selecting the source most nearlyproviding a voltage match with said load.

17. The combination claimed in claim 14 in which one of said storageelements has a large capacity to simulate a battery, and the other has asmaller value chosen to provide desired half-cycle resonance.

18. The combination claimed in claim 14, wherein said bilateral energytransfer circuit includes two pairs of transistors, each pair having theemitter of one transistor connected to the collector of the other,respectively, and

a common connection between one emitter of each pair of transistors andone end of said load.

19. A low loss rechargeable power s-upply for use with a loadcomprising, in combination, a source of voltage, a first rechargeablestorage element, a load, at least one transistor and one diode connectedbetween said first storage element and said load, a second rechargeablestorage element, and at least one transistor and one diode connectedbetween said second storage element and said load, and means foroperatively connecting said source of voltage to s-aid transistors.

20. A low loss rechargeable power supply system for 4use with a load,comprising, in combination, a plurality of storage elements fordelivering energy to said load, means for selectively connecting any oneof said storage elements to said load, and energy transfer circuitsconnected between said storage elements and said load for maintainingthe average energy and voltage of each of said storage elements at adesired equilibrium value.

21. A low loss power supply system in accordance with claim 1, whereinsaid constant current source comprises a voltage source in series withan in-ductance, said con stant current source being connected acrosssaid load.

References Cited UNITED STATES PATENTS 3,021,454 2/ 1962 PickensS17-148.5 3,143,668 y8/1964 Bloodworth et al. 307-885 3,158,791 11/1964Deneen et al 317-1485 3,183,412 5/1965 Arends 317-123 ARTHUR GAUSS,Primary Examiner. S. D. MILLER, Assistant Examiner.

1. A LOW LOSS POWER SUPPLY SYSTEM COMPRISING, IN COMBINATION, A SOURCEOF SUBSTANTIALLY CONSTANT CURRENT CONNECTED TO ONE TERMINAL OF A LOAD, ADIODE CONNECTED IN SERIES WITH A FIRST TRANSISTOR, THE SERIESCOMBINATION OF SAID DIODE AND SAID TRANSISTOR BEING CONNECTED ACROSS ANDLOAD, A SECOND TRANSISTOR CONNECTED IN SERIES WITH A VOLTAGE SUPPLY, ANDSAID LAST-NAMED SERIES COMBINATION BEING CONNECTED IN PARALLEL WITH THESERIES COMBINATION OF SAID DIODE AND SAID FIRST TRANSISTOR.